1. Field
Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.
2. Description of the Related Art
NAND type flash memories are known as electrically rewritable and highly integrable nonvolatile semiconductor memory devices. Memory transistors of conventional NAND type flash memories have a stacked-gate structure in which a charge accumulation layer (floating gate) and a control gate are stacked via an insulation film. A NAND cell unit is configured by a plurality of memory transistors connected in series in a column direction with adjoining ones sharing their source and drain, and select gate transistors provided at the ends of the column of memory transistors. One end of the NAND cell unit is connected to a bit line, and the other end thereof is connected to a source line. A memory cell array is configured by NAND cell units arranged in a matrix. NAND cell units arranged in a row direction are referred to as a NAND cell block. The gates of select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of memory transistors arranged in the same row are connected to the same word line. When N memory transistors are connected in series in the NAND cell unit, the number of word lines included in one NAND cell block is N.
As the size of such NAND type flash memory decreases, the distance between memory cells decreases in the NAND type flash memory, and this enhances the proximity effect caused by increase of inter-cell capacity of memory cells, which widens the distribution of a threshold value of a memory cell, and as a result, this enhances disturbs and makes it difficult to ensure various kinds of retention margins.
Additionally, as for these memory cells, simply stacking them means a simple increase in the number of step of manufacturing, and it is hence difficult to reduce the bit cost while ensuring an increase in the cell capacity that is balanced with the cost increase. Simple stacking is effective only by a bit cost shrink ratio=1/the number of stacked layers, i.e., the division by the number of layers, which means that the shrink ratio is small when the number of layers is large, leading to a high bit cost. Therefore, in the cell structure seeking a shrink by stacking, an object from a practical standpoint is to restrict the number of steps and the cost.